Today's advanced electronics, such as high definition televisions, place ever increasing demands on electronics. For example, customers demand HDTV display systems that can display images with more and more natural colors. Typical LCD drivers for driving pixel arrays of an LCD display use digital-to-analog converters to convert digital codes representing voltage levels to corresponding analog outputs. For example, sixteen binary numbers can be expressed using 4-bits to represent output voltages of the DAC. An actual analog output voltage Vout is proportional to an input binary number, and is expressed as a multiple of the binary number. When the reference voltage Vref of the DAC is a constant, the output voltage Vout has only a discrete value, e.g., one of 16 possible voltage levels, so that the output of the DAC is not truly an analog value. However, the number of possible output values can be increased by increasing the number of bits of input data. A larger number of possible output values in the output range reduces the difference between DAC output values.
It should be apparent that when the DAC input includes a relatively large number of bits, the DAC provides a relatively high-resolution output. However, the circuit area consumed by the DAC increases proportionally with resolution. An increase by only 1 bit in resolution doubles the area of the decoder in the DAC.
An example of a conventional R-type (resistive string) DAC structure used in a LCD source driver is shown in FIG. 1. More specifically, FIG. 1 shows a 6-bit DAC architecture. The DAC structure has a resistive string coupled between reference voltages V0 to V8. A resistor combination, and thus the voltage, is selected based on the 6-bit digital input D0 to D5. An operational amplifier is provided for increasing the driver current. The 6-bit DAC architecture requires 64 resistors, 64 signal lines and one 64x1 decoder. Using this standard architecture to fabricate an 8-bit DAC would require a four times (4×) increase in area, i.e., 256 resistors, 256 signal lines and one 256×1 decoder. Using this standard architecture, to fabricate a 10-bit DAC would require another four times (4×) increase in area, i.e., 1024 resistors, 1024 signal lines and one 1024×1 decoder. Thus, the 10-bit DAC would consume sixteen times as much chip or wafer area than a comparable 6-bit DAC. Traditional DAC architectures take up about 30% of the chip or wafer area. At increased resolutions (e.g., 10-bits and beyond), the size increases needed to achieve these resolutions are unacceptable.
A new DAC architecture for use in high resolution LCD source drivers is desired.